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DR SOUMEN MALLICK

ASSISTANT PROFESSOR

About

11-08-2010

EE

187682

O+

HINDUISM

1-443855943

20-01-2007

Qualifications

Educational Qualifications
  • PhD
  • National Institute of Technology Durgapur - 2019
  • M-tech
  • Jadavpur University - 2007
  • B-Tech
  • Haldia Institute of Technology - 2004
  • Higher Seondary
  • Simlapal Madan Mohan High School - 2000
  • Secondary
  • Pukhuria High School - 1997
Teaching and R & D experience
Teaching Research Industry
225 135 0

Promotions

Publications

Journal
Date Title Journal DOI Link
24-02-2022 Optimal design of second generation current conveyor using craziness-based particle swarm optimisation International Jounal of Bio-Inspired Computation DOI View
05-06-2017 SEOA based optimal design of analogue CMOS amplifier circuits International Journal of Bio-Inspired Computation DOI View
10-02-2017 Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization International Journal of Machine Learning and Cybernetics DOI View
03-07-2016 CMOS analogue amplifier circuits optimization using hybrid backtracking search algorithm with differential evolution Journal of Experimental & Theoretical Artificial Intelligence DOI View
02-03-2016 Optimal sizing and design of CMOS analogue amplifier circuits using craziness-based particle swarm optimization International Journal of Numerical Modelling: Electronic Networks, Devices and Fields DOI View
Conference
Date Title Conference DOI Link
23-04-2025 A DVCC based Realization of Optimized Fractional Step Low Pass Filter IEEE International Conference on Emerging Trends in Engineering and Medical Sciences DOI View
01-12-2024 Automated Design of CMOS-DACML Circuit 2024 IEEE International Conference on Communication Computing and Signal Processing (ICCCS) DOI View
23-10-2017 Sizing of two stage Op-Amp using OHS algorithm 2017 International Electrical Engineering Congress (iEECON) DOI View
23-10-2017 Optimal design of 5.5 GHz CMOS LNA using hybrid fitness based adaptive De with PSO 2017 International Electrical Engineering Congress (iEECON) DOI View
24-11-2016 CMOS analog amplifier circuit sizing using opposition based harmony search algorithm 2016 International Conference on Communication and Signal Processing (ICCSP) DOI View
Book Chapters
Date Title Book Title Editor ISBN DOI Link
23-08-2018 Optimal Design of 2.4 GHz CMOS LNA Using PSO with Aging Leader and Challenger Advances in Intelligent Systems and Computing Bhatia, S., Tiwari, S., Mishra, K., Trivedi, M. 978-981-13-0340-1 DOI View

Participations

Committee Name Start Date End Date
PCB AND CIRCUIT DESIGNING WORKSHOP 2025-26 03-02-2026 23-04-2026
INDUSTRY TALK #3 2025-26 MICROELECTRONICS 06-09-2025 23-04-2026
EE INDUSTRY TALK #2 2025-26 ENERGY SUSTAINABILITY 22-08-2025 23-04-2026
EE INDUSTRY TALK #1 2025-26 INDUSTRY 4.0 19-08-2025 23-04-2026
NAAC COMMITTEE 2025-26 01-07-2025 23-04-2026

Projects

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