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DR TRIBENI PRASAD BANERJEE

ASSOCIATE PROFESSOR

About

02-07-2013

ECE

125151

B+

HINDUISM

1-2328755844

02-07-2013

Qualifications

Educational Qualifications
  • Ph.D(ENGINEERING)
  • Jadavpur University - 2013
  • MTech
  • Jadavpur University - 2008
  • BE
  • Burdwan University - 2004
Teaching and R & D experience
Teaching Research Industry
200 108 48

Promotions

Publications

Journal
Date Title Journal DOI Link
14-06-2024 A dense sub-graph-based approach for automatic detection of optic disc International Journal of Bioinformatics Research Appllication DOI View
22-07-2022 Fault Signature Identification for BLDC motor Drive System-A Statistical Signal Fusion Approach Systems and Control DOI View
Conference
Date Title Conference DOI Link
09-10-2025 Design of a Precision Twin-T Notch Filter for 50Hz Noise Suppression International Conference on Computing, Intelligence, and Application (CIACON) DOI View
29-05-2025 Low-PDP 7:3-Counter with Novel Multi-threshold 2:1-Multiplexer IEEE Conference on Devices for Integrated Circuit (DevIC) DOI View
18-06-2020 Design and Analysis of Notch Depth for T-Notch Filter 2020 National Conference on Emerging Trends on Sustainable Technology and Engineering Applications (NCETSTEA) DOI View
Book Chapters
Date Title Book Title Editor ISBN DOI Link
29-05-2025 Area Efficient Lightweight Cipher System Implementation for Edge Device Bio-Inspired Computing of Springer Nature Bajaj, A., Abraham, A., Madhavi, K.R., Kriksciuniene, D. (eds) 978-3-031-78949-6 DOI View
01-08-2022 Introduction to Nano Electronics International Publication (AIP) 978-93-95978-32-3 DOI View
19-06-2020 Graph Based Approach for Image Data Retrieval in Medical Application Cognitive Computing in Human Cognition. Learning and Analytics in Intelligent Systems Mallick, P., Pattnaik, P., Panda, A., Balas, V. 978-3-030-48118-6 DOI View
13-12-2013 Intelligent Fault Tracking by an Adaptive Fuzzy Predictor and a Fractional Controller of Electromechanical System – A Hybrid Approach Lecture Notes in Computer Science of Springer International Publishing Switzerland Bijaya Ketan Panigrahi, IIT Delhi Electrical Engineering, Hauz Khas, 110016, New Delhi, India 978-3-319-03755-4 DOI View

Participations

Committee Name Start Date End Date
INDUSTRY INSTITUTE PARTNERSHIP CELL (CENTRAL) 01-07-2025 23-04-2026
DEPARTMENTAL MOOCS COMMITTEE 01-07-2024 23-04-2026
DEPARTMENTAL ALUMNI COMMITTEE 02-04-2024 23-04-2026
DEPARTMENTAL DISCIPLINARY COMMITTEE 02-04-2024 23-04-2026
DEPARTMENTAL SEMINAR WORKSHOP ORGANIZING COMMITTEE 02-04-2024 23-04-2026
TRAINING, MOOCS, HIGHER STUDIES 10-07-2018 23-04-2026

Projects

Project Name Start Date End Date Funded Funding Agency Agency Type Role Sanction Letter
Upgradation and modernization of the VLSI Lab (Phase II) to strengthen advanced teaching, hands-on training, and research in front-end and back-end VLSI design. The project focuses on updated EDA tools, enhanced FPGA/ASIC prototyping facilities, and an industry-aligned workflow environment. The objective is to build a robust ecosystem that supports UG/PG learning and faculty-led research in the VLSI domain. 12-01-2022 11-01-2024 Yes government Member Yes
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